/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_GMAC_HW_H
#define RK_GMAC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the GMAC.
 */
#define RK_GMAC_MAC_CONFIG_OFFSET                   0x0000U /* The MAC Configuration Register */
#define RK_GMAC_MAC_EXT_CONFIG_OFFSET               0x0004U /* The MAC Configuration Extended Register */
#define RK_GMAC_MAC_PKT_FILTER_OFFSET               0x0008U /* The MAC Packet Filter register */
#define RK_GMAC_MAC_WDT_TIMEOUT_OFFSET              0x000CU /* The Watchdog Timeout register */
#define RK_GMAC_MAC_HASH_TABLE0_OFFSET              0x0010U /* The Hash Table Register 0 */
#define RK_GMAC_MAC_HASH_TABLE1_OFFSET              0x0014U /* The Hash Table Register 1 */
#define RK_GMAC_MAC_HASH_TABLE2_OFFSET              0x0018U /* The Hash Table Register 2 */
#define RK_GMAC_MAC_VLAN_TAG_CTRL_OFFSET            0x0050U /* The VLAN Tag Control Register */
#define RK_GMAC_MAC_VLAN_TAG_DATA_OFFSET            0x0054U /* The VLAN Tag Data Register */
#define RK_GMAC_MAC_VLAN_HASH_TABLE_OFFSET          0x0058U /* The VLAN Hash Table Register */
#define RK_GMAC_MAC_VLAN_INCL_OFFSET                0x0060U /* The VLAN Tag Inclusion or Replacement Register */
#define RK_GMAC_MAC_INNER_VLAN_INCL_OFFSET          0x0064U /* The Inner VLAN Tag Inclusion or Replacement Register */
#define RK_GMAC_MAC_TX_FLOW_CTRL_OFFSET             0x0070U /* The Send Flow Control register */
#define RK_GMAC_MAC_RX_FLOW_CTRL_OFFSET             0x0090U /* The Receive Flow Control register */
#define RK_GMAC_MAC_RX_Q_CTRL4_OFFSET               0x0094U /* The Receive Queue Control 4 Register */
#define RK_GMAC_MAC_RX_Q_CTRL0_OFFSET               0x00A0U /* The Receive Queue Control 0 Register */
#define RK_GMAC_MAC_RX_Q_CTRL1_OFFSET               0x00A4U /* The Receive Queue Control 1 Register */
#define RK_GMAC_MAC_RX_Q_CTRL2_OFFSET               0x00A8U /* The Receive Queue Control 2 Register */
#define RK_GMAC_MAC_INTR_STATUS_OFFSET              0x00B0U /* The Interrupt Status Register */
#define RK_GMAC_MAC_INTR_ENABLE_OFFSET              0x00B4U /* The Interrupt Enable Register */
#define RK_GMAC_MAC_RX_TX_STATUS_OFFSET             0x00B8U /* The Receive Transmit Status Register */
#define RK_GMAC_MAC_PMT_CTRL_STATUS_OFFSET          0x00C0U /* The PMT Control and Status Register */
#define RK_GMAC_MAC_PWK_PKT_FILTER_OFFSET           0x00C4U /* The Remote Wakeup Filter Registers */

#define RK_GMAC_PWK_FILTER0_BMASK_OFFSET            0x00C4U /* RWK Filter 0 Byte Mask Registers */
#define RK_GMAC_PWK_FILTER1_BMASK_OFFSET            0x00C4U /* RWK Filter 1 Byte Mask Registers */
#define RK_GMAC_PWK_FILTER2_BMASK_OFFSET            0x00C4U /* RWK Filter 2 Byte Mask Registers */
#define RK_GMAC_PWK_FILTER3_BMASK_OFFSET            0x00C4U /* RWK Filter 3 Byte Mask Registers */
#define RK_GMAC_PWK_FILTER01_CRC_OFFSET             0x00C4U /* RWK Filter 0/1 CRC-16 Registers */
#define RK_GMAC_PWK_FILTER23_CRC_OFFSET             0x00C4U /* RWK Filter 2/3 CRC-16 Registers */
#define RK_GMAC_PWK_FILTER_OFFSET                   0x00C4U /* RWK Filter Offset Registers */
#define RK_GMAC_PWK_FILTER_COMMAND_OFFSET           0x00C4U /* RWK Filter Command Registers */

#define RK_GMAC_MAC_LPI_CTRL_STATUS_OFFSET          0x00D0U /* The LPI Control and Status Register */
#define RK_GMAC_MAC_LPI_TIMERS_CTRL_OFFSET          0x00D4U /* The LPI Timers Control register */
#define RK_GMAC_MAC_LPI_ENTRY_TIMER_OFFSET          0x00D8U /* The Tx LPI Entry Timer register */
#define RK_GMAC_MAC_LPI_1US_TICK_CNT_OFFSET         0x00DCU /* The generation of the Reference time Register */
#define RK_GMAC_MAC_PHYIF_CTRL_STATUS_OFFSET        0x00F8U /* PHY Interface Control and Status Register */
#define RK_GMAC_MAC_VERSION_OFFSET                  0x0110U /* The Version Register */
#define RK_GMAC_MAC_DEBUG_OFFSET                    0x0114U /* The Debug Register */
#define RK_GMAC_MAC_HW_FEATURE0_OFFSET              0x011CU /* The Features 0 Register */
#define RK_GMAC_MAC_HW_FEATURE1_OFFSET              0x0120U /* The Features 1 Register */
#define RK_GMAC_MAC_HW_FEATURE2_OFFSET              0x0124U /* The Features 2 Register */
#define RK_GMAC_MAC_HW_FEATURE3_OFFSET              0x0128U /* The Features 3 Register */
#define RK_GMAC_MAC_MDIO_ADDRESS_OFFSET             0x0200U /* The MDIO Address Register */
#define RK_GMAC_MAC_MDIO_DATA_OFFSET                0x0204U /* The MDIO Data Register */
#define RK_GMAC_MAC_ARP_ADDRESS_OFFSET              0x0210U /* The ARP Address register */
#define RK_GMAC_MAC_CSR_SW_CTRL_OFFSET              0x0230U /* The Software Programmable Control Register */
#define RK_GMAC_MAC_FPE_CTRL_STS_OFFSET             0x0234U /* The Frame Preemption Operation Control Register */
#define RK_GMAC_MAC_EXT_CFG1_OFFSET                 0x0238U /* The External Configuration 1 Register */
#define RK_GMAC_MAC_PRESN_TIME_NS_OFFSET            0x0240U /* The PTP System Time Register */
#define RK_GMAC_MAC_PRESN_TIME_UPDT_OFFSET          0x0244U /* The PTP System Time Update Register */
#define RK_GMAC_MAC_ADDRESS0_HIGH_OFFSET            0x0300U /* The MAC Address 0 High Register */
#define RK_GMAC_MAC_ADDRESS0_LOW_OFFSET             0x0304U /* The MAC Address 0 Low Register */

#define RK_GMAC_MMC_CONTROL_OFFSET                  0x0700U
#define RK_GMAC_MMC_RX_INTRRUPT_OFFSET              0x0704U
#define RK_GMAC_MMC_TX_INTRRUPT_OFFSET              0x0708U
#define RK_GMAC_MMC_RX_INTRRUPT_MASK_OFFSET         0x070CU
#define RK_GMAC_MMC_TX_INTRRUPT_MASK_OFFSET         0x0710U
#define RK_GMAC_TX_OCTET_CNT_OFFSET                 0x0714U /* The Number of Bytes Transmitted Register */
#define RK_GMAC_TX_PACKET_CNT_OFFSET                0x0718U /* The Number of Packets Transmitted Register */
#define RK_GMAC_TX_UNDERFLOW_ERROR_PACKET_OFFSET    0x0748U /* The Number of Packets of Transmitted with Underflow Error Register */
#define RK_GMAC_TX_CARRIER_ERROR_PACKET_OFFSET      0x0760U /* The Number of Packets of Transmitted with Carrier Error Register */
#define RK_GMAC_TX_OCTET_GOOD_CNT_OFFSET            0x0764U /* The Number of Bytes Transmitted Good Register */
#define RK_GMAC_TX_PACKET_GOOD_CNT_OFFSET           0x0768U /* The Number of Packets Transmitted Good Register */
#define RK_GMAC_TX_PAUSE_PACKET_OFFSET              0x0770U /* The Number of Pause Packets Transmitted Register */
#define RK_GMAC_RX_PACKET_CNT_OFFSET                0x0780U /* The Number of Packets Received Register */
#define RK_GMAC_RX_OCTET_CNT_OFFSET                 0x0784U /* The Number of Bytes Received Register */
#define RK_GMAC_RX_OCTET_GOOD_CNT_OFFSET            0x0788U /* The Number of Bytes Received Good Register */
#define RK_GMAC_RX_MULTICAST_PACKET_OFFSET          0x0790U /* The Number of Multicast Packets Received Register */
#define RK_GMAC_RX_CRC_ERROR_PACKET_OFFSET          0x0794U /* The Number of Packets of Received with CRC Error Register */
#define RK_GMAC_RX_PACKET_GOOD_CNT_OFFSET           0x07A8U /* The Number of Packets Received Good Register */
#define RK_GMAC_RX_LEN_ERROR_PACKET_OFFSET          0x07C8U /* The Number of Packets of Received with Length Error Register */
#define RK_GMAC_RX_PAUSE_PACKET_OFFSET              0x07D0U /* The Number of Pause Packets Received Register */
#define RK_GMAC_RX_FIFO_OVERFLOW_PACKET_OFFSET      0x07D4U /* The Number of Packets Received with FIFO Overflow Register */
#define RK_GMAC_RX_WATCHDOG_ERROR_PACKET_OFFSET     0x07D4U /* The Number of Packets Received with Watchdog Error Register */
#define RK_GMAC_MMC_IPC_RX_INTRRUPT_MASK_OFFSET     0x0800U
#define RK_GMAC_MMC_IPC_RX_INTRRUPT_OFFSET          0x0808U
#define RK_GMAC_RX_IPV4_PACKET_OFFSET               0x0810U /* The Number of IPv4 Packets Received Register */
#define RK_GMAC_RX_IPV4_HEADER_ERROR_PACKET_OFFSET  0x0814U /* The Number of IPv4 Packets Received with Header Error Register */
#define RK_GMAC_RX_IPV6_PACKET_OFFSET               0x0820U /* The Number of IPv6 Packets Received Register */
#define RK_GMAC_RX_IPV6_HEADER_ERROR_PACKET_OFFSET  0x0824U /* The Number of IPv6 Packets Received with Header Error Register */
#define RK_GMAC_RX_UDP_ERROR_PACKET_OFFSET          0x0834U /* The Number of UDP Packets Received Error Register */
#define RK_GMAC_RX_TCP_ERROR_PACKET_OFFSET          0x083CU /* The Number of TCP Packets Received Error Register */
#define RK_GMAC_RX_ICMP_ERROR_PACKET_OFFSET         0x0844U /* The Number of ICMP Packets Received Error Register */
#define RK_GMAC_RX_IPV4_HEADER_ERROR_OCTET_OFFSET   0x0854U /* The Number of Bytes Received with IPv4 Packet Header Error Register */
#define RK_GMAC_RX_IPV6_HEADER_ERROR_OCTET_OFFSET   0x0868U /* The Number of Bytes Received with IPv4 Packet Header Error Register */
#define RK_GMAC_RX_UDP_ERROR_OCTET_OFFSET           0x0874U /* The Number of Bytes Packets Received UDP Packet Error Register */
#define RK_GMAC_RX_TCP_ERROR_OCTET_OFFSET           0x087CU /* The Number of Bytes Packets Received TCP Packet Error Register */
#define RK_GMAC_RX_ICMP_ERROR_OCTET_OFFSET          0x0884U /* The Number of Bytes Packets Received ICMP Packet Error Register */
#define RK_GMAC_MMC_FPE_TX_INTRRUPT_OFFSET          0x08A0U
#define RK_GMAC_MMC_FPE_TX_INTRRUPT_MASK_OFFSET     0x08A4U
#define RK_GMAC_MMC_TX_FPE_FRAGMENT_CNTR_OFFSET     0x08A8U
#define RK_GMAC_MMC_TX_HOLD_REQ_CNTR_OFFSET         0x08ACU
#define RK_GMAC_MMC_FPE_RX_INTRRUPT_OFFSET          0x08C0U
#define RK_GMAC_MMC_FPE_RX_INTRRUPT_MASK_OFFSET     0x08C4U
#define RK_GMAC_MMC_RX_PACKET_ASM_ERR_CNTR_OFFSET   0x08C8U
#define RK_GMAC_MMC_RX_PACKET_ASM_SMD_CNTR_OFFSET   0x08CCU
#define RK_GMAC_MMC_RX_PACKET_ASSEMBLY_CNTR_OFFSET  0x08D0U
#define RK_GMAC_MMC_RX_FPE_FRAGMENT_CNTR_OFFSET     0x08D4U

#define RK_GMAC_MAC_L3_L4_CTRL0_OFFSET              0x0900U /* The Layer 3 and Layer 4 Control 0 Register */
#define RK_GMAC_MAC_LAYER4_ADDR0_OFFSET             0x0904U /* The MAC Layer 4 Address 0 Register */
#define RK_GMAC_MAC_LAYER3_ADDR0_REG0_OFFSET        0x0910U /* The MAC Layer 3 Address 0 Register 0 */
#define RK_GMAC_MAC_LAYER3_ADDR1_REG0_OFFSET        0x0914U /* The MAC Layer 3 Address 1 Register 0 */
#define RK_GMAC_MAC_LAYER3_ADDR2_REG0_OFFSET        0x0918U /* The MAC Layer 3 Address 2 Register 0 */
#define RK_GMAC_MAC_LAYER3_ADDR3_REG0_OFFSET        0x091CU /* The MAC Layer 3 Address 3 Register 0 */
#define RK_GMAC_MAC_TIMESTAMP_CTRL_OFFSET           0x0B00U /* The MAC System Time Generator Register */
#define RK_GMAC_MAC_SUB_SECOND_INC_OFFSET           0x0B04U /* The MAC System Time Increment Register */
#define RK_GMAC_MAC_SYS_TIME_SEC_OFFSET             0x0B08U /* The MAC System Time Seconds Register */
#define RK_GMAC_MAC_SYS_TIME_NS_OFFSET              0x0B0CU /* The MAC System Time Nanoseconds Register */
#define RK_GMAC_MAC_SYS_TIME_SEC_UPDATE_OFFSET      0x0B10U /* The MAC System Time Seconds Update Register */
#define RK_GMAC_MAC_SYS_TIME_NS_UPDATE_OFFSET       0x0B14U /* The MAC System Time Nanoseconds Update Register */
#define RK_GMAC_MAC_TS_ADDRESS_OFFSET               0x0B18U /* The Timestamp Address Register */
#define RK_GMAC_MAC_TS_STATUS_OFFSET                0x0B20U /* The Timestamp Status Register */
#define RK_GMAC_MAC_TX_TS_NS_OFFSET                 0x0B30U /* The Nanoseconds part of Timestamp for Tx PTP Packets Register */
#define RK_GMAC_MAC_TX_TS_SEC_OFFSET                0x0B34U /* Teh Seconds part of Timestamp for Tx PTP Packets Register */
#define RK_GMAC_MAC_AUXILIARY_CONTROL_OFFSET        0x0B40U /* The Auxiliary Timestamp Control Register */
#define RK_GMAC_MAC_AUXILIARY_TS_NS_OFFSET          0x0B48U /* The Auxiliary Nanoseconds part of Timestamp Register */
#define RK_GMAC_MAC_AUXILIARY_TS_SEC_OFFSET         0x0B4CU /* The Auxiliary Seconds part of Timestamp Register */
#define RK_GMAC_MAC_TS_INGRESS_CORRECT_NS_OFFSET    0x0B58U
#define RK_GMAC_MAC_TS_EGRESS_CORRECT_NS_OFFSET     0x0B5CU
#define RK_GMAC_MAC_TS_INGRESS_LATENCY_OFFSET       0x0B68U /* The Ingress MAC Latency Register */
#define RK_GMAC_MAC_TS_EGRESS_LATENCY_OFFSET        0x0B6CU /* The Egress MAC Latency Register */
#define RK_GMAC_MAC_PPS_CONTROL_OFFSET              0x0B70U /* The PPS Control Register */
#define RK_GMAC_MAC_PPS0_TARGET_TIME_SEC_OFFSET     0x0B80U /* The PPS Target Time Seconds Register */
#define RK_GMAC_MAC_PPS0_TARGET_TIME_NS_OFFSET      0x0B84U /* The PPS Target Time Nanoseconds Register */
#define RK_GMAC_MAC_PPS0_INTERVAL_OFFSET            0x0B88U /* The PPS Interval Register */
#define RK_GMAC_MAC_PPS0_WIDTH_OFFSET               0x0B8CU /* The PPS Width Register */

#define RK_GMAC_MTL_OPERATION_MODE_OFFSET           0x0C00U /* The Operation Mode Register */



#define RK_GMAC_DMA_MODE_OFFSET                     0x1000U /* The DMA Bus Mode Register */
#define RK_GMAC_DMA_SYSBUS_MODE_OFFSET              0x1004U /* The DMA System Bus Mode Register */
#define RK_GMAC_DMA_INTERRUPT_STATUS_OFFSET         0x1008U /* The DMA Interrupt Status Register */
#define RK_GMAC_DMA_DEBUG_STATUS0_OFFSET            0x100CU /* The DMA Debug Status 0 Register */
#define RK_GMAC_AXI_LPI_ENTRY_INTERVAL_OFFSET       0x1040U /* The AXI LPI Entry Interval Register */
#define RK_GMAC_DMA_TBS_CTRL_OFFSET                 0x1050U /* The DMA TBS Attributes Control Register */

#ifdef __cplusplus
}
#endif

#endif /* RK_GMAC_HW_H */